The present invention relates generally to an apparatus and method for electrical signal amplification, and more particularly to an apparatus and method for utilizing a correction loop amplifier in conjunction with a main signal amplifier to reduce output signal distortion.
Signal amplifiers are used in many types of electronic circuits in a wide variety of consumer, industrial and other products. One such application is a power amplifier that may be used to provide a large amount of signal amplification for audio equipment. A conventional prior art differential input power amplifier circuit is illustrated in FIG. 1. One problem with this circuit, however, is that it typically has relatively high total harmonic distortion (xe2x80x9cTHDxe2x80x9d), and thus its direct use in high performance circuits is limited.
One approach to reducing the THD in a power amplifier circuit is taught by above-referenced U.S. patent application Ser. No. 09/491,543. FIG. 2 illustrates a low THD amplifier circuit 100 as disclosed by the above-referenced patent application. The transfer function of this circuit is generally given by                                                                         v                O                            =                                                                                                                                            A                          m                                                ⁡                                                  (                          s                          )                                                                    ⁡                                              [                                                                                                                                            A                                c                                                            ⁡                                                              (                                s                                )                                                                                      ⁢                                                          (                                                              1                                -                                k                                                            )                                                                                +                          k                                                ]                                                              ⁢                                          v                                              I                        +                                                                              -                                                                                    A                        m                                            ⁡                                              (                        s                        )                                                              ⁢                                          kv                                              I                        -                                                                                                                                                                                A                        m                                            ⁡                                              (                        s                        )                                                              ⁢                                                                  A                        c                                            ⁡                                              (                        s                        )                                                              ⁢                                          (                                              1                        -                        k                                            )                                        ⁢                                          k                      2                                                        +                                                            A                      m                                        ⁡                                          (                                              1                        -                        k                                            )                                                        +                  1                                                                                                        =                                                                                          [                                              1                        +                                                  k                                                                                    A                              m                                                        ⁡                                                          (                              s                              )                                                                                                                          ]                                        ⁢                                          v                                              I                        +                                                                              -                                                            k                                                                                                    A                            c                                                    ⁡                                                      (                            s                            )                                                                          ⁢                                                  (                                                      1                            -                            k                                                    )                                                                                      ⁢                                          v                                              I                        -                                                                                                                                  k                    2                                    +                                      1                                                                  A                        c                                            ⁡                                              (                        s                        )                                                                              +                                      1                                                                                            A                          m                                                ⁡                                                  (                          s                          )                                                                    ⁢                                                                        A                          c                                                ⁡                                                  (                          s                          )                                                                    ⁢                                              (                                                  1                          -                          k                                                )                                                                                                                                                    (        1        )            
where       k    =                  R        2                              R          1                +                  R          2                      ,            k      2        =                  R        4                              R          3                +                  R          4                      ,
Am(s) and Ac(s) are transfer functions of main amplifier 102 and correction loop amplifier 104, respectively.
Generally, to properly operate circuit 100, the output of correction amplifier 104 (Ac(s)) should be virtual ground. If the input is a completely fully differential signal (i.e., v1+=v1xe2x88x92) the following equations may be derived:                                                         v              O                        ⁢                                          R                4                                                              R                  3                                +                                  R                  4                                                              =                      v                          I              +                                      ,                              and            ⁢                          xe2x80x83                        ⁢                          v              O                                =                                                                      R                  2                                                  R                  1                                            ⁢                              (                                                      v                                          I                      +                                                        -                                      V                                          I                      -                                                                      )                                      =                                                            2                  ⁢                                      R                    2                                                                    R                  1                                            ⁢                                                v                                      I                    +                                                  .                                                                        (        2        )                                                      Thus:                    ⁢                      xe2x80x83                    ⁢                                    2              ⁢                              R                2                                                    R              1                                      =                                                            R                3                            +                              R                4                                                    R              4                                .                                    xe2x80x83            
Furthermore, if R4=R1, then R3=2R2xe2x88x92R1.
In practical circuit design, it is generally difficult to match R3=2R2xe2x88x92R1 to other resistors with values of R1 or R2.
If Am(s) greater than  greater than 0, Ac(s) greater than  greater than 0 and Ac(s)(1xe2x88x92k) greater than  greater than 0, the above equation may be simplified to                               v          O                =                                            v                              I                +                                                    k              2                                =                                                                                          R                    3                                    +                                      R                    4                                                                    R                  4                                            ⁢                              xe2x80x83                            ⁢                              v                                  I                  +                                                      =                                          (                                                                            R                      3                                                              R                      4                                                        +                  1                                )                            ⁢                              v                                  I                  +                                                                                        (        3        )            
This indicates that the output voltage vo is mainly determined by the positive input v1+, and is insensitive to the negative input v1xe2x88x92. Essentially, the circuit may be operating as a single ended system, in which the input is v1+ and the output is vo. Therefore, a potential disadvantage with this circuit is that it may not be operating as a fully differential structure. Generally, in a mixed-signal environment, many of the digital noises are present in the power supply, substrate, or the signal wires, in a common mode fashion. In such an environment, a fully differential structure generally provides high (digital) noise immunization, a high Common-Mode Rejection Ratio (xe2x80x9cCMRRxe2x80x9d), and a high Power Supply Rejection Ratio (xe2x80x9cPSRRxe2x80x9d). However, because of the potential singled-ended operating characteristic of the circuit of FIG. 2, the benefits of a fully differential circuit may not be achieved.
For the circuit configuration shown in FIG. 2, the CMRR is:                     CMRR        =                                            A              DM                                      A              CM                                =                                                                      v                  O                                /                                  (                                                            v                                              I                        +                                                              -                                          v                                              I                        -                                                                              )                                                                                                  v                    O                                    /                                      (                                                                  v                                                  I                          +                                                                    +                                              v                                                  I                          -                                                                                      )                                                  /                2                                      =                                          1                2                            =                                                -                  6                                ⁢                                  xe2x80x83                                ⁢                dB                                                                        (        4        )            
Another potential disadvantage with the circuit illustrated in FIG. 2 is that it is relatively difficult to add a filtering function to the circuit.
These problems are generally solved or circumvented, and technical advantages are generally achieved, by preferred embodiments of the present invention comprising an apparatus and method for utilizing a correction loop amplifier in conjunction with a main amplifier to produce signal amplification with very low THD. The correction amplifier preferably has one input directly coupled to a first input of the main amplifier, and an output coupled to a second input of the main amplifier via a resistor. The second input of the correction amplifier is preferably coupled to a signal input via a voltage divider or RC network. Alternatively, the second input of the correction amplifier may be coupled to ground, typically for a single ended input negative gain configuration. A preferred embodiment configuration provides a power amplifier with improved THD over prior art circuits. The circuit is very flexible, and may incorporate low, high or band pass filter functions if desired. In addition, the power amplifier may be implemented in any combination of single or differential inputs and outputs.
In accordance with a preferred embodiment of the present invention, a power amplifier circuit apparatus comprises a main amplifier having first and second input nodes and an output node; a feedback resistor coupled between the first input node and the output node of the main amplifier; a correction loop amplifier having first and second input nodes and an output node, wherein the first input node of the correction amplifier is coupled to the first input node of the main amplifier; and a resistor coupled between the output node of the correction amplifier and the second input node of the main amplifier.
In accordance with another preferred embodiment of the present invention, a differential output amplifier circuit generates a balanced output signal having positive and negative signal components. The circuit comprises a first power amplifier circuit for providing the positive signal component of the balanced output signal, and a second power amplifier circuit for providing the negative signal component of the balanced output signal. Each of the first and second power amplifier circuits are configured similarly to the previously described embodiment.
In accordance with another preferred embodiment of the present invention, an amplifier circuit comprises a main amplifier and a correction amplifier, the main amplifier having first and second input nodes and an output node, and the correction amplifier having first and second input nodes and an output node. A method of correcting distortion in the amplifier circuit comprises feeding back an output signal from the main amplifier output node to the main amplifier first input node via a first resistor; feeding back the output signal to the correction amplifier first input node via the resistor; generating a correction signal at the output node of the correction amplifier; and providing the correction signal to the main amplifier second input node via a second resistor.
An advantage of a preferred embodiment of the present invention is that it provides much improved CMRR performance over prior art approaches. Assuming, ideal matching of resistors, and ideal main and correction amplifiers, the CMRR of the circuit should approach infinity. Practically, the CMRR of the circuit is limited by the matching of the resistors and the CMRR of the amplifiers. The higher CMRR generally provides higher immunization to digital interference and other common mode noise.
A further advantage of a preferred embodiment of the present invention is that it provides more gain flexibility than prior art approaches. The gain may be any value that is determined by             R      2              R      1        ,
so this preferred embodiment may be used to implement, for example, the volume control in the feedback loop of amplifier. For the prior art scheme discussed hereinabove, with                     v        O                    v                  I          +                      =                            R          3                          R          4                    +      1        ,
the minimum gain value is 1. Because the gain cannot be less than 1, it generally cannot be used in a volume control application.
A further advantage of a preferred embodiment of the present invention is that it provides configuration flexibility. For example, the amplifier could be configured to perform:
(1) fully-differential (balanced) input, single-ended output, 2-channel (4-channel) stereo;
(2) single-ended input, single-ended output, 2-channel (4-channel) stereo;
(3) fully-differential (balanced) input and output, mono (2-channel stereo);
(4) single-ended input, fully-differential (balanced) output, mono (2-channel stereo).
Configuration selection may be performed during design, or by using a few switches, after the circuit has been built. A basic design may be prepared beforehand, and then implemented in different configurations with a few wire connection changes.
A further advantage of a preferred embodiment of the present invention is that it is relatively easy to match all of the resistors, because each of the resistors is assigned one of two values.
A further advantage of a preferred embodiment of the present invention is that it is easy to extend the circuit to perform low pass, high pass, or band pass filter functions.
A further advantage of a preferred embodiment of the present invention is that it has extremely low THD compared with a conventional amplifier configuration.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.